Many different types of memory devices are used with electronic devices such as computers, personal digital assistants (PDAs), digital cameras, and cellular phones. The memory devices include, for example, random-access memory (RAM), read only memory (ROM), synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), and flash memory, as described, for example, in U.S. Pat. No. 5,677,556 and US published application 2006/0278913 A1, both of which are incorporated herein by reference in their entirety.
Flash memory is a type of non-volatile memory that can be rewritten electronically for multiple times. Typical flash memory devices are based on MOSFET technologies having architectures similar to those of NOR or NAND gates.
Thin-film transistors (TFTs) can be employed in NAND type or NOR type memory devices. Unlike conventional MOSFETs that use a bulk semiconductor material as the substrate, a TFT has a thin film semiconductor active layer over a dielectric layer, which can be deposited over a variety of semiconductor, insulating or conductive substrates.
NAND flash memory devices typically include multiple strings of memory cells. A conventional string of memory cells is fabricated on a substrate, such as a p-type silicon substrate. Multiple n+ regions in a p-type substrate or in p-well in the substrate act as source and drain regions for the cells. Each memory cell has a floating gate formed over a tunnel dielectric layer and configured to store electrical charge. Control gates, formed over a blocking dielectric layer over the floating gates, are used to control reading, writing (programming), or erasing processes of the memory cells.
The drain side of the NAND string can be connected to the bit line through a selection transistor. The source side of the NAND string can be connected to a source line through another selection transistor. The control gates of an array of memory cells in the row direction can serve as a word line.
The write operation can be sequentially performed to a memory cell at the source line. A high voltage (about 20 V) is applied to the control gate of the selected memory cell. An intermediate voltage (about 10 V) can be applied to the control gates and unselected wordlines of the memory cells on the bit line side. If a voltage of 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell to cause charge injection from the substrate to the floating gate through the dielectric tunnel layer. After the charge injection, the threshold of the selected memory cell is shifted in the positive direction, and the state of the cell can be identified through its increased threshold voltage. The intermediate voltage does not cause the charge injection, and thus the not-selected cells have an unchanged threshold value.
Erase operation can be performed for a plurality of cells at the same time. For example, all the control gates can be set to 0 V, and a high voltage of 20 V can be applied on the p-well. Select gates and bit lines are left floating. Negative charges in the floating gates can thus be released to the substrate, and the threshold value is shifted to the negative direction.
During a read operation, a voltage of 0.1-1.2 V can be applied to the bit line and the control and selection gates of the cells in unselected NAND memory blocks, and a voltage of 0 V is applied to the source line and to the control gate of the selected memory cell, while unselected wordlines in selected NAND memory blocks have a voltage of about 3-8 V. If a current flow is detected at the selected cell, then the selected cell is read as the “1” state.